Hello, I’ve been trying to decide on a FPGA development board, and have only been able to find posts and Reddit threads from 4-5 years ago. So I wanted to start a new thread and ask about the best “mid-range” FGPA development board in 2018. (Price range $100-$300.) I started with this Quora answer about FPGA boards, from 2013. The Altera DE1 sounded good. Then I looked through the Terasic DE boards. Then I found this Reddit thread from 2014, asking about the DE1-SoC vs the Cyclone V GX Starter Kit: https://www.reddit.com/FPGA/comments/1xsk6w/cyclone_v_gx_starter_kit_vs_de1soc_board/ (I was also leaning towards the DE1-SoC.) Anyway, I thought I better ask here, because there are probably some new things to be aware of in 2018. I’m completely new to FPGAs and VHDL, but I have experience with electronics/microcontrollers/programming. My goal is to start with some basic soft-core processors. I want to get some C / Rust programs compiling and running on my own CPU designs. I also want to play around with different instruction sets, and maybe start experimenting with asynchronous circuits (e.g. clock-less CPUs) Also I don’t know if this is possible, but I’d like to experiment with ternary computing, or work with analog signals instead of purely digital logic. EDIT: I just realized that you would call those FPAAs, i.e. “analog” instead of “gate”. Would be cool if there was a dev board that also had an FPAA, but no problem if not. EDIT 2: I also realized why "analog signals on an FPGA" doesn't make any sense, because of how LUTs work. They emulate boolean logic with a lookup table, and the table can only store 0s and 1s. So there's no way to emulate a transistor in an intermediate state. I'll just have play around with some transistors on a breadboard. UPDATE: I've put together a table with some of the best options:
A very simple FPGA development board that plugs into a Raspberry Pi, so you have a "backup" hard-core CPU that can control networking, etc. Supports a huge range of pmod accessories. You can write a program/circuit so that the Raspberry Pi CPU and the FPGA work together, similar to a SoC. Proprietary bitstream is fully reverse engineered and supported by Project IceStorm, and there is an open-source toolchain that can compile your hardware design to bitstream. Has everything you need to start experimenting with FPGAs.
Xilinx Zynq 7-Series SoC - ARM Cortex-A9 processor, and Artix-7 FPGA. 125 IO pins. 1GB DDR2 RAM. Texas Instruments WiLink 8 wireless module for 802.11n Wi-Fi and Bluetooth 4.1. No LEDs or buttons, but easy to wire up your own on a breadboard. If you want to use a baseboard, you'll need a snickerdoodle black ($195) with the pins in the "down" orientation. (E.g. The "breakyBreaky breakout board" ($49) or piSmasher SBC ($195)). The snickerdoodle one only comes with pins in the "up" orientation and doesn't support any baseboards. But you can still plug the jumpers into the pins and wire up things on a breadboard.
Has one of the latest Xilinx SoCs. 2 GB (512M x32) LPDDR4 Memory. Wi-Fi / Bluetooth. Mini DisplayPort. 1x USB 3.0 type Micro-B, 2x USB 3.0 Type A. Audio I/O. Four user-controllable LEDs. No buttons and limited LEDs, but easy to wire up your own on a breadboard
Xilinx Zynq 7000 SoC (ARM Cortex-A9, 7-series FPGA.) 1 GB DDR3 RAM. A few switches, push buttons, and LEDs. USB and Ethernet. Audio in/out ports. HDMI source + sink with CEC. 8 Total Processor I/O, 40 Total FPGA I/O. Also a faster version for $299 (Zybo Z7-20).
Same as DE10-Standard, but not as many peripherals, buttons, LEDs, etc.
icoBoard ($100). (Buy it here.) The icoBoard plugs into a Raspberry Pi, so it's similar to having a SoC. The iCE40-HX8K chip comes with 7,680 LUTs (logic elements.) This means that after you learn the basics and create some simple circuits, you'll also have enough logic elements to run the VexRiscv soft-core CPU (the lightweight Murax SoC.) The icoBoard also supports a huge range of pluggable pmod accessories:
numato Mimas A7 ($149). An excellent development board with a Xilinx Artix 7 FPGA, so you can play with a bigger / faster FPGA and run a full RISC-V soft-core with all the options enabled, and a much higher clock speed. (The iCE40 FPGAs are a bit slow and small.)
I ordered a iCE40-HX8K Breakout Board to try out the IceStorm open source tooling. (I would have ordered an icoBoard if I had found it earlier.) I also bought a numato Mimas A7 so that I could experiment with the Artix 7 FPGA and Xilinx software (Vivado Design Suite.)
What can I do with an FPGA? / How many LUTs do I need?
VexRiscv is "A FPGA friendly 32 bit RISC-V CPU implementation." This is a RISC-V implementation written in SpinalHDL. VexRiscv has a lot of plugin and configuration options. The Murax SoC is a very light SoC that can run on an iCE40-HX8k (but probably not the 1k FPGA that only has 1,280 LUTs). The Briey SoC only runs on Xilinx or Altera FPGAs.
Why I see Virtcoin as a $200 coin when really considering ASIC resistance
First of all, Vertcoin does indeed have a tremendous community, and this is not to be understated. However, this is only a fraction of the value position of this coin. I just want to expand on the ASIC resistance thing a bit. As an electrical engineer who has actually designed ASIC's, I do have some background on this. What I can tell you is that this term "ASIC Resistant" is that it is a little bit misleading. In theory, any algorithm can be turned into an ASIC. An ASIC or Application Specific Integrated Circuit is a digital or analog or mixed analog digital circuit that has been cast into Sea of Gates, Semi-Custom, or Full Custom ASIC technology. The cheapest route is Sea of Gates. If one didn't want to do a Sea of Gates ASIC, they could implement an algorithm in a FPGA, or Field Programmable Gate Array. Altera and Xilinx are the dominant players here. In the early days of Bitcoin, there were many FPGA miners, this was a very common way to mine Bitcoin. Overall, It takes somewhere between USD $50,000 to $1,000,000 to make an ASIC. It's an expensive process. There is a tremendous amount of engineering, where the circuit is designed in System Verilog, Verilog or VHDL, and very extensive testbenches to make sure that the when the chip is made it works the first time. Engineers prototype ASICs in FPGA's, and the development boards for ASIC emulation can cost $20k or more just in themselves. Then the design goes to a foundry where the chip is made, and that will be expensive, $50k to $500k. So there has to be motivation to make an ASIC, such as high volume chip sales. For Sea of Gates technology, a rule of thumb is that there is typically a break even point when a company sells 1,000 to 2,000 chips a year that has been made into an ASIC. That is because Sea of Gates is about a $100k process. The ASIC Resistance of Vertcoin is not technology related, i.e. the algorithm that is currently being used could be made into an ASIC. What makes Vertcoin ASIC resistance is the commitment of the team to change the algorithm if someone does make an ASIC to mine Vertcoin. This is what gives Vertcoin it's value position. I really appreciate that! This is a de-facto way to limit the power of miners, in one simple swipe. How wants to deal with this Bitcoin forking situation anymore? At this point, with the upcoming fork, it seems more and more unnecessary. I see Bitcoin as a storage of value layer, and other coins such as VTC and LTC as transaction layer coins. To me what gives VTC value is the intention of the community AND the consequent action of it.
Continued fromhttp://www.reddit.com/Bitcoin/comments/1e5qim/reverse_engineering_of_avalon_asic_chip_work_in/ You guys convinced me that the best way to achieve the goals stated in the previous post is to design the ASIC chip from scratch, or based on a FPGA VHDL design, instead of reverse engineering it. Here is a reference to a relevant FPGA design opensource resource : https://github.com/fpgamineOpen-Source-FPGA-Bitcoin-Miner And also the original FPGA which the Avalon ASIC is the evolution for, and for which there are schematics and documentation available at : https://github.com/ngzhang/Icarus So i'm offering a 100 BTC tip to anyone who can put out a VHDL Bitcoin miner working design conforming to the avalon specs at https://github.com/BitSyncom/avalon-ref/ Thank you in advance for your response! This is an amazing community! Cheers EDIT Opensourcing the ASIC chip design is indeed something that will happen according to our roadmap and milestones reached. At any further revision of the chip the previous generation would be opensourced. Added link to FPGA github resource mentioned in the comments. Since i received several critics regarding the size of the tip/bounty, i have modified the amount a bit. Thank you!
FPGA Bitcoin Mining. At the foundation of block creation and mining is the calculation of this digital signature. Different cryptocurrencies use different approaches to generate the signature. For the most popular cryptocurrency, Bitcoin, the signature is calculated using a cryptographic hashing function. For those unfamiliar with cryptographic hashes, hashes calculate a fixed-length unique ... Since I have been playing about with bitcoin mining for the last few weeks, it has given me the opportunity to look at some of the publicly available source code. We decided to take a gander at the communication channels used to communicate the results back from the FPGA’s to the master computers. On the whole the code is mostly abysmal…., seemingly written by people that have absolutely ... 4. Bitcoin Miner on an FPGA All the FPGA implementation was done using the hardware description language VHDL. As a golden model, a software Java implementation was also created. To calculate the hash, we divide the block header in 16 slices with 32 bytes each and use them as serialized input in the same block of logic. This way we reduce the ... BTC-FPGA-MINER - Open Source FPGA Bitcoin Miner. Overview News Bugtracker Downloads. Project maintainers. lama, lama; Details . Name: btcfpgaminer Created: May 2, 2014 Updated: Jul 2, 2017 SVN Updated: May 15, 2014 SVN: Browse Latest version: download (might take a bit to start...) Statistics: View Bugs: 1 reported / 0 solved. Star 2 you like it: star it! Other project properties. Category ... Stratix IV FPGA Open-Source Bitcoin Miner. OrphanedGland ([email protected])Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP. In this fork I have added ...
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